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Enhanced Data Integrity

Introduction

The properties of NAND flash memory make it ideal for applications that require high integrity while operating in challenging environments. The integrity of data to NAND flash memory is generally maintained through ECC algorithms, bad block management, and power failure recovery. Flash controllers can support at least 8 bits ECC capability for data integrity and lifetime improvement. The bad block management is also included the mechanism of power failure recovery which integrate the wear leveling algorithm to rebuild the data during power on initialization.

The Need for Data Retention
Data retention refers to the ability of a memory bit to retain its data state over long periods of time regardless of whether the part is powered on or powered off. Intrinsically, it is referring to the length of time the charge stays on a floating gate. On the other hand, when considering data retention in real-world operation conditions, data retention has be measured extrinsically including the endurance as well as the number of cycles a flash device can be programmed and erased without failure. For a NAND device, instead of a single bit, a string of bits has to be read at one time. Typically, an entire page is read sequentially. As a consequence, an error could impact the state of the other bits being read. So, even though intrinsically data retention is a long period of time, the ability to read it successfully each time depends on the read error rate. Therefore, error detection and correction scheme is necessary.

The Need for ECC
Random read errors are commonplace in the use of NAND flash. Therefore, it is essential to preserve data integrity. Error Checking and Correction (ECC) plays such an important role to identify and correct errors during read or write operations to NAND flash. This mechanism is able to correct errors within its capability. If occurred errors are too many to handle, the information will not be able to retrieve successfully.

The Need of Bad Block management
NAND flash memory incorporates a certain percentage of bad blocks, and most NAND flash manufacturers indicate that 98% of the total blocks could be in normal state for a brand new NAND flash memory. These blocks are taken as bad and should not be programmed or erased any further. Bad block management functions automatically identify, on initialization, where the bad blocks are located and map them out of the array. The maps are updated over time to incorporate any of additional bad blocks as the memory is used, and these specified blocks are instructed not to use for storage.

The Need for Power Failure Recovery
When utilizing flash memory devices, it is a problem to deal with potentially intermittent power sources or power availability. As flash memory is non-volatile, it will not be affected by loss of power once data is stored . However, as data operation in progress, the flash memory can be left in an incomplete state by a power loss event. To prevent data loss from events like that, it is necessary to prepare power loss recovery routines enabling the flash memory device through a power loss recovery cycle to check for incomplete operations upon power up to finish or correct them if possible.
 

Advantages

  • Guarantee correctness
  • Enhance availability on information transaction
  • Reduce data loss in time
  • Sustain state of retrievable information

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